MAP = """++++ Click to expand regmap |
|< 100% 5% 5% 5% 25% 5% 5% 50% >|
|Address ||Bits |Name |Type |Default |Description |
|DWORD |BYTE |::: |::: |::: |::: |::: |
^0x0000 ^0x0000 ^REG_VERSION ^^^^Version and Scratch Registers ^
| | |[31:0] |VERSION[31:0] |RO |0x00000000 |Version number. Unique to all cores. |
^0x0001 ^0x0004 ^REG_ID ^^^^Version and Scratch Registers ^
| | |[31:0] |ID[31:0] |RO |0x00000000 |Instance identifier number. |
^0x0002 ^0x0008 ^REG_SCRATCH ^^^^Version and Scratch Registers ^
| | |[31:0] |SCRATCH[31:0] |RW |0x00000000 |Scratch register. |
^0x0003 ^0x000c ^REG_CONFIG ^^^^Version and Scratch Registers ^
| | |[0] |IQCORRECTION_DISABLE |RO |0x0 |If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) |
|::: |::: |[1] |DCFILTER_DISABLE |RO |0x0 |If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) |
|::: |::: |[2] |DATAFORMAT_DISABLE |RO |0x0 |If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) |
|::: |::: |[3] |USERPORTS_DISABLE |RO |0x0 |If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) |
|::: |::: |[4] |MODE_1R1T |RO |0x0 |If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet) |
|::: |::: |[5] |DELAY_CONTROL_DISABLE |RO |0x0 |If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) |
|::: |::: |[6] |DDS_DISABLE |RO |0x0 |If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) |
|::: |::: |[7] |CMOS_OR_LVDS_N |RO |0x0 |CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance) |
|::: |::: |[8] |PPS_RECEIVER_ENABLE |RO |0x0 |If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) |
|::: |::: |[9] |SCALECORRECTION_ONLY |RO |0x0 |If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) |
|::: |::: |[12] |EXT_SYNC |RO |0x0 |If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. |
|::: |::: |[13] |RD_RAW_DATA |RO |0x0 |If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel. |
^0x0004 ^0x0010 ^REG_PPS_IRQ_MASK ^^^^PPS Interrupt mask ^
| | |[0] |PPS_IRQ_MASK |RW |0x1 |Mask bit for the 1PPS receiver interrupt |
^0x0007 ^0x001c ^REG_FPGA_INFO ^^^^FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_intel_device_info_enc.tcl |Intel encoded values]] [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]] ^
| | |[31:24] |FPGA_TECHNOLOGY |RO |0x0 |Encoded value describing the technology/generation of the FPGA device (arria 10/7series) |
|::: |::: |[23:16] |FPGA_FAMILY |RO |0x0 |Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) |
|::: |::: |[15:8] |SPEED_GRADE |RO |0x0 |Encoded value describing the FPGA's speed-grade |
|::: |::: |[7:0] |DEV_PACKAGE |RO |0x0 |Encoded value describing the device package. The package might affect high-speed interfaces |
^Tue Mar 14 10:17:59 2023 ^^^^^^
++++"""

from pynq import Overlay
overlay = Overlay("/home/D/projects/rru4044_top.bit")

# help(overlay)

